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Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry and critical AI infrastructure. The company operates across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
As Physical Design Manager, you will lead the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning through timing signoff and GDSII tapeout. You'll sit at the intersection of custom ASIC design and hardware-algorithm co-designed systems, shaping physical feasibility early in the design cycle by collaborating closely with RTL and architecture teams. Your responsibilities span the full backend implementation flow—optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets.
Key responsibilities include:
- Leading and hiring the Physical Design team, providing individual guidance and performance feedback
- Creating work estimates and schedules to support aggressive tapeout plans
- Specifying and negotiating EDA tools to support physical design methodology
- Collaborating with RTL, architecture, and DFT teams on early floorplanning, macro placement, and physical feasibility
- Leading the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, CTS, and P&R
- Owning static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes
- Driving physical optimization for power, performance, area (PPA), power integrity (IR/EM), and crosstalk analysis
- Executing full chip/block physical signoff checks (DRC, LVS, ERC, antenna fixes)
- Creating and executing tapeout checklists, managing final stream-out processes, and supporting post-silicon physical debugging and bring-up
You will thrive in a cross-functional environment, taking pride in tapeout-proven execution and maintaining clarity in fast-paced build cycles.
REQUIREMENTS:
- Minimum 7 years of managerial experience
- Track record of leading at least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes
- Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure
- Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations
- Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility
BONUS QUALIFICATIONS:
- Experience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles
- Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration)
- Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows
