SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Salary: USD 141,150 - 211,400 / annual
Marvell's Central Engineering team is seeking a Senior Staff Engineer specializing in high-speed IC package signal integrity (SI) and power integrity (PI) design. You will contribute to the development of advanced microelectronic packages for semiconductors supporting 448 Gb/s data rates and beyond.
In this role, you will operate independently in technically ambiguous areas, identifying gaps and developing improved approaches when established methodologies do not exist. Key responsibilities include:
• Package interconnect design, modeling, and characterization for high-speed interfaces
• Power delivery network (PDN) design and analysis
• SI/PI simulation methodology development and correlation with lab measurements
• Development of design rules and practical solutions for custom high-speed interfaces
• Cross-functional collaboration to explore new interconnect architectures
• Investigation of channel and PDN behavior to establish root causes of performance issues
• Lab measurements and validation using equipment such as VNA and TDR
• Automation of SI, PI, and packaging activities using scripting tools
• Management of package development involving assembly, physical layout, analog/digital design, and marketing teams
You will work within Marvell's central advanced packaging organization, which plays a critical role in delivering next-generation connectivity and compute products. This position directly shapes product performance, reliability, and time-to-market, making it a key contributor to Marvell's technology leadership.
REQUIREMENTS:
• MS or PhD in Electrical Engineering or Computer Engineering with relevant industry experience
• Strong understanding of transmission line theory and electromagnetic fundamentals
• Deep understanding of frequency and time domain analysis in high-speed design
• Demonstrated ability to independently solve complex SI/PI problems
• Experience driving SI/PI design from architecture through implementation and validation
• Experience developing SI/PI workflows and investigating tool trade-offs
• Proficiency with 2D and 3D EM simulation tools (Ansys HFSS, SI-Wave, Cadence Clarity)
• Power plane design, modeling, and analysis using tools like PowerSI and Siwave
• Working knowledge of channel and circuit simulators (ADS, Hspice)
• Proven track record of systematically investigating channel/PDN behavior
• Experience with lab measurements and equipment (VNA, TDR)
• Familiarity with layout tools (Allegro, APD, PADS)
• Strong communication, presentation, and documentation skills
HIGHLY DESIRED:
• Familiarity with packaging technologies, materials, package substrate design rules, and assembly rules
• Knowledge of thermal and mechanical analysis of IC package development
• Experience with high-speed electronic packaging for digital and analog ICs
• Experience with 2.5D/3D package development
• Experience with CPC/CPO connectors
• Ability to automate SI, PI, and packaging activities using Python or similar scripting tools
• Experience managing package development across cross-functional teams
