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Liquid AI, spun out of MIT CSAIL, builds general-purpose AI systems optimized to run efficiently across deployment targets—from data center accelerators to on-device hardware—ensuring low latency, minimal memory usage, privacy, and reliability. The company partners with enterprises in consumer electronics, automotive, life sciences, and financial services.
You will be the first hire to build Liquid's partner silicon program from scratch. This role owns the device lab, profiling process, and technical relationships with partner engineering teams. Approximately 70% of the work is hands-on technical; the remainder involves partner- and customer-facing engagement, starting with automotive OEMs and expanding to PC OEMs.
Key responsibilities include:
- Owning and managing the partner device lab, handling every SoC that Qualcomm, AMD, Intel, NVIDIA, and other edge/physical AI chip makers ship to Liquid
- Lowering Liquid Foundation Models onto partner silicon and profiling speed, latency, power, and thermal characteristics
- Working directly with partner customer engineers to co-create demos and benchmark narratives
- Presenting results to partners and demand-side buyers, explaining competitive advantages of LFMs on their silicon
- Flagging model and runtime performance gaps to the Edge Inference team with clear hardware-level diagnoses
- Contributing to runtime and model-level optimization where capability allows
You will work daily with Liquid's Edge Inference team, who own the runtime fixes you identify. This role requires physical presence in the office (Boston or San Francisco) due to hardware ownership and lab management responsibilities.
REQUIREMENTS
Must-have:
- Hands-on experience deploying and profiling ML models on at least one edge SoC family (Qualcomm Snapdragon/Hexagon, AMD Ryzen AI/XDNA, Intel NPU, SiMa.ai MLSoC, or comparable)
- Working knowledge of at least one vendor lowering and runtime toolchain (Qualcomm AI Engine Direct/QNN, SiMa Palette, OpenVINO, ONNX Runtime execution providers, or similar)
- On-device performance measurement expertise: latency, throughput, power, and thermal
- Comfort presenting technical results to external engineers and commercial stakeholders
Nice-to-have:
- Breadth across two or more chipset families
- Experience inside a chip vendor's customer-engineering, field-application, or AI-enablement team
- Runtime or kernel-level optimization experience
