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Fractile is building specialized hardware to accelerate AI inference at scale. Founded in 2022, the company has raised $220M from top-tier investors (Founders Fund, Accel) and is focused on solving the latent bottleneck in frontier AI: inference speed. The company designs chips and systems optimized for generating outputs at thousands of tokens per second while handling long-context model complexity.
You will join as a Lead RTL Designer with deep expertise in datapath performance, power, and area (PPA) optimization. This is a senior individual contributor role with full agency to drive RTL design and microarchitectural decisions end-to-end. You will own datapath PPA closure, from identifying bottlenecks to proposing RTL changes to validating impact against targets.
Key responsibilities:
- Drive datapath microarchitecture decisions: pipelining, retiming, and parallelism-vs-area trade-offs
- Own PPA closure end-to-end on production compute silicon
- Translate PPA targets into concrete RTL and microarchitectural decisions
- Write timing-aware datapath RTL and iterate against synthesis/STA feedback to close critical paths
- Collaborate with physical design engineers on PPA closure
- Validate formal verification and equivalence checking
- Work cross-functionally with hardware, software, silicon, and modeling teams on rapid iteration cycles
The culture emphasizes ownership, rapid iteration directly with leadership, full-stack engagement across hardware and software, and pragmatic execution on ambitious timelines.
REQUIREMENTS:
- Strong datapath microarchitecture background: pipelining, retiming, and parallelism-vs-area trade-offs for PPA
- Track record of driving datapath PPA closure end-to-end: identifying bottlenecks, proposing RTL changes, and validating impact against targets
- Good knowledge of fixed-point, floating-point, and/or quantized arithmetic design
- Deep understanding of PPA trade-off analysis and ability to translate PPA targets into concrete RTL and microarchitectural decisions
- Experience with low-power design techniques
- Experience writing timing-aware datapath RTL and iterating against synthesis/STA feedback to close timing on critical paths
- Familiarity with synthesis tools (e.g., Synopsys Design Compiler/Fusion Compiler, Cadence Genus) and datapath IP/generator libraries (e.g., DesignWare)
- Demonstrated, measurable PPA improvements delivered on production datapath or compute silicon
- Experience with formal verification or equivalence checking
- Physical design awareness sufficient to collaborate effectively with PD engineers on PPA closure
NICE TO HAVE:
- Experience with AI/ML accelerator datapath (e.g., systolic arrays, MAC/tensor engines) or other high-performance compute chip architectures
- Experience with static timing analysis tools (e.g., PrimeTime, Tempus)
