SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry and critical AI infrastructure. The company operates across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
As a Lead RTL Design Engineer, you will lead and own the design of digital logic at the heart of Normal's thermodynamic hardware, working at the intersection of classical ASIC design and novel computing architectures. You will drive RTL design from microarchitecture through tapeout, including writing microarchitecture specifications, creating synthesizable SystemVerilog, collaborating with verification engineers on comprehensive testing (conventional and formal methods), and working with physical design to meet area and timing constraints.
Key responsibilities include:
- Leading and organizing the RTL design team, setting standards and high expectations while fostering a collaborative, execution-focused environment
- Creating and enforcing RTL coding standards; writing and owning synthesizable RTL in SystemVerilog across datapath logic, control, and memory interfaces
- Translating high-level architecture specifications into implementable microarchitectures
- Partnering with verification teams on verification plans, debug support, and coverage closure
- Collaborating with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT
- Participating in design reviews and contributing to architecture decisions beyond implementation
- Supporting tapeout preparation, establishing tapeout criteria, signing off on readiness, and supporting post-silicon bring-up
Because Normal's chips are not standard accelerators, the Lead RTL engineer operates closer to first-principles decisions than at larger companies, shaping architecture rather than just implementing it.
REQUIREMENTS:
- Proven experience leading an RTL design team through multiple tapeouts (block and top-level work)
- Hands-on production RTL experience in SystemVerilog with closure through synthesis and place-and-route for multiple blocks and designs
- Experience working on datapaths, pipelines, or custom logic where microarchitecture was not fully specified upfront
- Strong debugging instincts across simulation, waveforms, and formal counterexamples
- Ability to work directly with architects and physical designers
BONUS QUALIFICATIONS:
- Experience at an AI chip company with tightly coupled design and verification
- Multiple interface architecture experience (PCIe, Ethernet, memory devices)
- FPGA familiarity
- Experience with AI-assisted RTL or EDA tooling
- Exposure to physical design constraints, floorplanning, or timing-driven RTL development
