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FPGA Digital Design Engineer

Kepler Communications - Remote - Remote - posted 2026-10-16

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Kepler Communications operates the first commercial optical data relay constellation with 33 satellites launched to date, providing real-time on-orbit connectivity for critical missions. We are seeking an experienced FPGA Digital Design Engineer to develop the next generation of our satellites. You will work with a small dedicated team of engineers building Kepler spacecraft, responsible for designing and implementing FPGA code with focus on either DSP algorithms for modulating and demodulating signals on our software-defined radio (SDR), or embedded systems interfacing with processors and peripherals. You will participate in all phases of the FPGA design flow including simulation, synthesis, place & route, timing closure, and hardware testing. Key Responsibilities: - Develop custom IP for new features of Kepler satellite digital payloads - Iterate on current DSP and interface designs to improve reliability - Work with IP core vendors to integrate new functionality into Kepler designs - Collaborate with lead engineers in developing communications and network architecture for the future satellite constellation - Participate in conceptual design studies of new spacecraft Requirements: - Bachelor's Degree in Computer Engineering, Electrical Engineering, or equivalent - 5+ years of working experience with FPGA/RTL design - Proficiency in Verilog, SystemVerilog, or VHDL with willingness to learn or pivot to SystemVerilog - Experience with Xilinx FPGAs, specifically Zynq and UltraScale - Solid understanding of timing principles, including clock domain crossing and timing closure - Strong scripting skills (Python, Tcl, csh/bash, etc.) - Experience with FPGA tools (Vivado, Quartus) and HDL simulation tools (ModelSim) Bonus qualifications include: Master's degree in Computer/Electrical Engineering, experience with coherent digital demodulation (BPSK, QPSK, QAM), memory-mapped interfaces (AXI, Wishbone, Avalon), high-speed transceivers (JESD204B, PCIe, SATA), linting tools (Questa Sim, Riviera-Pro), Xilinx Versal and RFSoC, PCB design experience, and RF electronics knowledge.

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