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Salary: USD 100,000 - 500,000 / annual
Tenstorrent is seeking a Formal Verification Engineer to ensure the correctness of next-generation high-performance RISC-V CPUs and AI compute platforms. In this role, you will use formal methods to prove complex hardware behavior, uncover corner cases that simulation may miss, and provide architects and RTL designers with confidence in design correctness. You'll work closely with CPU architects, RTL designers, and other DV engineers to develop properties, build formal verification environments, analyze failures, and drive issues to closure. This is a hands-on opportunity to apply formal techniques to challenging problems in modern processor design.
You will gain deep experience applying formal verification to high-performance, out-of-order RISC-V CPU designs, learn how to identify which hardware behaviors are best verified through formal methods versus simulation and emulation, and develop expertise in writing scalable properties and proofs for complex control logic and interacting microarchitectural blocks. You'll also learn how architectural intent translates into formal properties, assumptions, and measurable verification goals, while working alongside world-class CPU architects and RTL engineers on next-generation processors for AI, HPC, and high-performance computing.
Tenstorrent is a company leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. The team has developed a high-performance RISC-V CPU from scratch and shares a passion for AI and a deep desire to build the best AI platform possible. The company values collaboration, curiosity, and a commitment to solving hard problems.
**Requirements:**
- 6+ years of experience in design verification, formal verification, or related RTL verification for CPUs, SoCs, ASICs, or complex digital designs
- Hands-on experience with formal verification methodologies and tools, including property checking, assertions, assumptions, constraints, and coverage analysis
- Strong SystemVerilog skills, including experience writing and debugging SVA (SystemVerilog Assertions)
- Solid understanding of digital design and computer architecture; experience with CPU pipelines, caches, interfaces, control logic, or other complex microarchitecture is highly valuable
- Strong programming and scripting skills in Python, Tcl, C/C++, or similar, with excellent debugging and problem-solving abilities
- Ability to think about hardware behavior in terms of properties, invariants, assumptions, assertions, and proofs
- Strong debugging skills to analyze counterexamples, understand RTL behavior, and determine root causes of failures
