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Ricursive Intelligence is a frontier AI lab building self-improving systems for chip design, backed by $335M from Sequoia, Lightspeed, DST, and NVIDIA Ventures. The company combines exceptional talent—including IMO, IPHO, and IOAA gold medalists, chip design pioneers (AlphaChip, ePlace, RL-CCD, INSTA, C3PO), and leaders from Apple Silicon, Google TPU, Anthropic, Google DeepMind, Stanford, and MIT—to reinvent chip development by closing the loop between AI and hardware.
As DFT Engineer, you will own Design-for-Test end-to-end at Ricursive: architecting scan, MBIST, and boundary-scan infrastructure for complex chips at advanced nodes; defining fault models and coverage strategies; generating and signing off test patterns; and leading post-silicon bring-up with foundry and OSAT partners. You will work directly with RTL, DV, and physical design engineers, flex into RTL and DV work as needed, and integrate AI tools into traditional DFT flows to accelerate development and improve silicon quality.
Key responsibilities include:
- Owning DFT architecture and insertion for complex silicon: hierarchical scan and compression, BIST, MBIST and BISR planning and repair, boundary scan, and IJTAG networks (IEEE 1149.1), integrated with synthesis, physical design, and STA flows from RTL to GDS.
- Defining fault-model and coverage strategy (stuck-at, transition, path-delay, cell-aware, bridging) and owning ATPG generation, fault simulation, coverage closure, pattern verification, and DFT signoff to tapeout, balancing coverage, test time, pattern count, and area.
- Driving post-silicon test from first silicon to production: ATE pattern conversion and bring-up, CP (wafer sort), FT, and SLT program development and debug, scan diagnosis, failure analysis, and yield/DPPM improvement with foundry and OSAT partners.
- Integrating DFT with RTL, DV, and physical design: setting DFT requirements at micro-architecture stage, verifying test logic alongside functional verification, closing test-mode timing, and taking on RTL design and DV work directly when needed.
- Making DFT AI-native: shaping how AI plans, closes, and debugs DFT, measured in coverage, test time, and DPPM.
- Partnering cross-functionally on chip design infrastructure and automation, encoding DFT knowledge as reusable flows, checks, and evaluation targets.
You will have the opportunity to define foundational DFT methodology and infrastructure from the ground up as part of a small, high-impact team.
REQUIREMENTS:
- BS in Electrical Engineering, Computer Engineering, Computer Science, or closely related technical field.
- 5+ years of hands-on DFT experience owning the full lifecycle on complex SoCs or IPs: DFT architecture and specification, scan and compression insertion, MBIST and BISR, boundary scan and IJTAG, test-mode timing constraints, DFT verification and DRC closure, fault-model and coverage analysis, ATPG pattern generation and signoff.
- Day-one fluency in at least one production DFT stack and gate-level simulation, with strong Tcl and Python scripting and sufficient Verilog/SystemVerilog to write and debug test logic and testbenches.
- Post-silicon experience on production silicon: converted and brought up ATPG and MBIST patterns on ATE, debugged CP, FT, and SLT failures, worked directly with foundry and OSAT partners.
- Practical, demonstrated use of AI coding and agentic tools in your own engineering work, with clear ideas about where they help in DFT flows and where they do not.
PREFERRED QUALIFICATIONS:
- Masters or PhD in EE, CE, CS, or related field with focus on VLSI test, fault tolerance and reliability, or EDA/CAD algorithms.
- Deep expertise in high-performance compute silicon (ML accelerators, CPUs, GPUs, large SoCs), including DFT for advanced packaging.
- Product and test engineering depth: test program development, characterization and screens (HVS, HTOL), yield analytics and wafer-map correlation, outlier screening, RMA and failure analysis.
- Demonstrated and quantified gains from AI/ML in chip design or test flow; experience building or extending AI-assisted design and verification flows.
- Publications at major conferences (ITC, VTS, DAC, ICCAD, DATE) or open-source contributions in DFT, test, or AI for chip design.
