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Salary: USD 209,300 - 313,900 / annual
Nuvia, now part of Qualcomm, is reimagining silicon and creating computing platforms to transform the industry. As a CPU Physical Design CAD Engineer at the Senior Staff level, you will build and support world-class implementation tools and flows for custom CPUs, ensuring industry-leading power, performance, and area metrics.
You will develop, integrate, and release new features in high-performance place-and-route CAD flows, architecting and recommending methodology improvements across the silicon design process. Your responsibilities include maintaining and debugging implementation flows, resolving project-specific issues, and working closely with worldwide CPU physical design teams to provide methodology guidance and tools/flows support. You will collaborate with EDA vendors to define roadmap priorities and resolve tool issues, helping achieve class-leading PPA (power, performance, area) outcomes.
This role offers the opportunity to work with some of the most talented engineers in the world on designs that push the envelope on performance and energy efficiency. You will have significant technical scope and influence over the company's silicon implementation strategy and tooling infrastructure.
QUALIFICATIONS:
Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in related field with 5+ years of relevant experience. OR PhD in related field with 4+ years of relevant experience.
Preferred: Master's degree in Electrical/Electronics Engineering or Computer Science; 10+ years of hands-on experience in place-and-route of high-performance chips (design or CAD role); high proficiency in Tcl and Python; experience with automation; broad experience across physical design tasks (place-and-route, analysis, timing sign-off, PDV); experience with advanced technology nodes (5nm or lower); solid understanding of digital design, timing analysis, and physical verification; strong expertise with industry-standard place-and-route tools such as Cadence Innovus; proven track record of managing and regressing place-and-route flows.
