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Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry and critical AI infrastructure. The company operates across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
As a Compiler Backend Engineer, you will design and build custom compilation that maps large language model inference onto Normal's specialized hardware. The hardware executes memory-bound inference operations inside memory itself rather than shuttling weights to a processor, requiring a novel compiler backend that cannot be borrowed from existing CPU or GPU toolchains.
You will own multiple critical areas:
**Code Generation**: Build compilation passes that transform lowered programs into hardware-executable code, designing novel compilation approaches where conventional methods don't apply. Success means correct and efficient code for every operation the models require.
**Scheduling and Memory Planning**: Own how work and data are scheduled and placed across the hardware's resources, optimized for utilization and end-to-end latency on LLM inference.
**Fusion and Dispatch**: Make fusion and dispatch decisions for LLM inference to maximize compute time and minimize data movement.
**Hardware Co-Design**: Work at the abstraction layer between compiler and hardware, feeding compiler constraints back to hardware architects while the design can still evolve.
**Profiling and Validation**: Validate every optimization with measured results from simulators, FPGA prototypes, and silicon. Maintain a performance regression suite the team trusts.
**Cross-Team Handoffs**: Collaborate with frontend compiler engineers to decide which operations the compiler generates versus which use hand-tuned kernels.
You will work with pre-silicon hardware, measuring your work against simulators and FPGA prototypes first, then against silicon as it arrives. This role sits at the boundary between compiler and hardware, requiring judgment about which optimizations belong at different layers.
**Requirements:**
- Deep experience with compiler optimization or code generation for accelerators or non-CPU targets (scheduling, tiling, fusion, resource allocation)
- Comfort working close to hardware; think in terms of memory bandwidth and utilization as well as asymptotic complexity
- Willingness to design compilation approaches from first principles when existing ones don't fit
- Track record of shipping optimizations that moved measured performance numbers
- Comfort building software for hardware still in evolution, from simulation through bring-up
- Fluency in Python; familiarity with C, C++, or Rust
**Bonus qualifications:**
- Experience with PyTorch's compilation stack (TorchDynamo, FX, Inductor, torch.export) or other ML compilers (IREE, TVM, XLA)
- Experience compiling for in-memory, spatial, or other non-von-Neumann compute targets
- Background in hardware design tools (logic synthesis, place-and-route)
- Experience with cycle-level or performance simulators to guide optimization
- Open-source contributions to compiler or kernel infrastructure (PyTorch, Triton, TVM, MLIR, LLVM)
- Publications or presentations on compiler or performance work at MLSys, ASPLOS, or CGO
