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Axiado is an AI-enhanced security processor company building silicon-rooted security and management chips for AI data center infrastructure. The company combines platform security, BMC/firmware, and on-chip AI for real-time threat detection and dynamic power/thermal management. Founded in 2017 with 100+ employees, Axiado recently closed a $100M+ Series C+ round and is scaling rapidly.
You will work across the full ML stack from model to silicon, optimizing training and inference performance on GPU and AI-accelerator infrastructure. This role uniquely bridges algorithm work, systems-level software, and infrastructure—closing the loop end-to-end rather than owning a single layer. You'll have rare access to the full cycle of AI silicon development, from model design through chip deployment.
Key responsibilities include:
- Optimizing training and inference performance across GPU and AI-accelerator infrastructure, including MLOps pipelines
- Designing, training, and evaluating ML models (deep learning, LLM, computer vision, or recommendation systems) and taking them into production
- Building or optimizing inference engines and serving runtimes against real hardware constraints (latency, memory, power)
- Working in depth on at least one specialty area: NPU hardening, systems-level software, inference engines, test/verification harnesses, or security-focused ML
- Collaborating closely with RTL/hardware, firmware, and QA teams to ship AI features end-to-end from training through deployment and monitoring
Requirements:
- 3–5+ years of hands-on AI/ML experience; Bachelor's degree required, Master's preferred
- Hands-on experience with AI/ML infrastructure and performance (GPU clusters, distributed training, inference-serving optimization, MLOps pipelines)
- Model and algorithm development experience (designing, training, and evaluating ML models)
- Experience taking models into production (feature engineering, data pipelines, deployment)
- AI chip and hardware-aware ML experience (optimizing inference engines for specific chips, or adapting model architecture/quantization to chip constraints)
- Hands-on experience in at least one of these five specialty areas:
• NPU/AI-accelerator: hardening or extending an NPU core into production silicon, mapping models onto MAC/tensor-engine constraints, or NPU-aware RTL/DV work
• Systems/sys-level software: BMC firmware, embedded Linux, RTOS (e.g., Zephyr), or other low-level system software
• Inference engine/runtime: built or materially optimized an inference engine or serving runtime against real hardware constraints
• Test/verification harness: built an automated harness that closes a loop (e.g., agent-driven RTL/DV test runner or hardware bring-up/MFG test harness)
• Cybersecurity: AI-driven log/intrusion analysis, AI-assisted penetration testing, or firmware/hardware security
