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Salary: USD 180,000 - 255,000 / annual
SambaNova Systems is seeking a Principal RTL Design Engineer to own the design, integration, and implementation of high-speed IO and memory subsystems within the DataScale platform. This is a hands-on, high-ownership role central to delivering reliable, high-performance AI infrastructure at scale.
You will drive these subsystems across the full product lifecycle, from architecture exploration and microarchitecture definition through RTL and integration of internal and third-party IP (PCIe, Ethernet, CXL, HBM, die-to-die). You will engage directly with system and chip architects on feasibility studies and design trade-off analysis to meet PPA constraints. You will own microarchitecture specification and deliver synthesizable, high-quality SystemVerilog RTL for assigned blocks against functionality, performance, and power targets.
Key responsibilities include running the front-end design flow end-to-end (lint, CDC/RDC, synthesis, timing constraint development, design-for-test readiness), partnering with STA and physical design teams on timing closure and optimization at advanced process nodes, and collaborating with verification, emulation, software, and firmware teams. You will drive cross-functional triage of complex functional and performance issues to root cause and closure, apply engineering best practices including code review and testing, and improve design and integration methodology and flow scalability.
This role is based in Austin, Texas or San Jose, California.
REQUIREMENTS:
- MS in Electrical Engineering, Computer Science, or related field
- 7+ years of experience in ASIC design
- Experience in logic design, microarchitecture, specification, SystemVerilog RTL design, and functional verification
- Experience with power, performance, or area optimization
- Experience with two or more on-chip or chip-to-chip protocols and interfaces (AXI, APB, PCIe, Ethernet, UCIe)
- Experience with memory subsystems such as HBM and CXL
- Ability to evaluate and select vendor IP, and to read and distill complex IP and protocol specifications into actionable design requirements
- Clear and effective communication with proactive, collaborative problem-solving approach
PREFERRED QUALIFICATIONS:
- Experience taking one or more ASIC products from concept to silicon
- Familiarity with emerging scale-up protocols (ESUN, SUE, UAL) and scale-out protocols such as Ultra Ethernet
- Experience designing on-chip interconnect and traffic-management logic (NoC fabrics, switches, arbiters, QoS, congestion control)
- Knowledge of machine learning and hardware accelerator architectures
