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Jariet Technologies, Inc. (a CesiumAstro subsidiary) is seeking a Principal ASIC Design Engineer - Chip Lead to lead the development of next-generation high-speed mixed-signal and DSP communications chips. The role requires cradle-to-grave expertise across the full IC/ASIC design lifecycle, from concept through production release.
You will own large, complex communications chip designs and demonstrate mastery across multiple disciplines: digital communications systems, DSP architecture, ASIC microarchitecture, analog IP integration, embedded processors, high-level verification, RTL design with asynchronous clock domains, timing analysis, design-for-test (DFT), backend flow, chip bring-up, lab debug, and volume production transition. This is a technical leadership role where you will drive architectural decisions, mentor engineers, and interface with cross-functional teams including backend, verification, and customer-facing groups.
The ideal candidate combines deep technical expertise with strong program management and people leadership skills. You will analyze specifications at the architecture and micro-architecture level to identify design improvements, communicate with customers, and support marketing and sales interactions. Experience with advanced front-end design flows, high-speed analog block integration, constraint-driven verification methodologies (UVM, VMM, OVM, SPECMAN), Verilog/SystemVerilog, synthesis, formal verification, and static timing analysis (STA) is essential. DSP block implementation and low-power design flows are highly desirable.
Note: This position requires U.S. citizenship or eligible immigration status per U.S. Government Space Technology Export Regulations (8 U.S.C. 1324b(a)(3)).
REQUIREMENTS:
- Master's degree in Engineering with minimum 10 years of experience
- Proven IC/ASIC development experience from concept through production silicon release
- Advanced front-end design flow expertise: system simulation, RTL implementation, verification, synthesis, backend team interfacing
- High-speed analog block integration into digital logic
- Strong architecture and micro-architecture analysis skills to identify design improvements
- Excellent program management, people management, and project tracking abilities
- Customer communication and marketing/sales interaction experience
- ASIC verification using constraint-driven coverage methodologies (UVM, VMM, OVM, SPECMAN)
- Fluency in Verilog and SystemVerilog; synthesis, formal verification, and STA flow expertise
- Highly desirable: low-power design flows, DSP block implementation
- U.S. citizenship or lawful permanent resident status required
