SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Salary: USD 110,000 - 170,000 / annual
Arista Networks is seeking an FPGA Design Engineer to join the Hardware Design Engineering team, which develops high-speed networking and Ethernet products for enterprise campuses, hyperscaler data centers, and AI clusters. You will be a core member of the FPGA Design and Verification team, responsible for developing high-performance control path FPGAs that power Arista's flagship data center platforms.
In this role, you will own the full design lifecycle from gathering architectural requirements and reviewing board schematics through rigorous verification, system bring-up, and production deployment. You will work closely with cross-functional hardware, software, and manufacturing engineering teams to innovate new system architectures and drive FPGA development from concept to delivery.
Key responsibilities include:
- RTL Development & Verification: Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation
- FPGA Flow Implementation: Execute the full FPGA development flow, including synthesis, place and route, timing closure, and in-system hardware debugging
- System-Level Integration: Collaborate with hardware and software teams to drive rapid bring-up and debugging of next-generation network switch platforms
- Design & Architecture Reviews: Participate in peer RTL code reviews, PCB schematic reviews, and board design reviews
- Toolchain Automation: Develop Python, Tcl, or shell scripts to streamline data processing and automate FPGA design workflows
You will gain expertise in switching architectures (data and control path), critical I/O interfaces (PCIe, Interlaken, Ethernet PHY/MAC, SMBus, SPI, MDIO, JTAG), Ethernet-based protocols (PTP, sFlow, PoE), real-world design challenges (timing closure, resource optimization, clock domain crossing), multi-vendor FPGA ecosystems, and cross-functional system design including PCB schematic interpretation and advanced simulation frameworks.
Qualifications:
- 5+ years of hands-on experience in Verilog/SystemVerilog RTL design
- Proven background in Control Path design
- Direct experience with On-Chip Bus interfaces (I2C, SPI, MDIO, PCIe, AXI)
- Local to the Bay Area
Preferred:
- Experience with Ethernet Data Path architecture and design
- Hands-on experience with Streaming Bus interfaces (AXI-Stream)
- Background in FPGA resource management and timing closure
- Proficiency in Python, Tcl, or general scripting for EDA tool automation
- Lab debugging & validation experience with logic analyzers, oscilloscopes, and vendor-specific debug tools
