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FPGA Design Engineer

Arista Networks - Santa Clara, CA, United States - In-office - posted 2026-10-09

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Salary: USD 110,000 - 170,000 / annual

Arista Networks is seeking an FPGA Design Engineer to join its Hardware Design Engineering team, which develops high-speed networking and Ethernet products for enterprise campuses, hyperscaler data centers, and AI clusters. You will be a core member of the FPGA Design and Verification team, responsible for developing high-performance control path FPGAs that power Arista's flagship data center platforms. You will own the full design lifecycle from architectural requirements and board schematic review through rigorous verification, system bring-up, and production deployment. Key Responsibilities: - Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL code with custom testbench creation - Execute the complete FPGA development flow including synthesis, place and route, timing closure, and in-system hardware debugging - Collaborate with hardware and software engineering teams to drive rapid bring-up and debugging of next-generation network switch platforms - Participate in peer RTL code reviews and PCB schematic/board design reviews - Develop Python, Tcl, or shell scripts to automate FPGA design workflows and streamline data processing You will gain expertise in switching architectures (data and control paths), Ethernet-based protocols (PTP, sFlow, PoE), real-world FPGA engineering challenges (timing closure, resource optimization, clock domain crossing), multi-vendor FPGA ecosystems, and cross-functional system design involving complex PCB schematics and advanced simulation frameworks. Requirements: - 5+ years of hands-on experience in Verilog/SystemVerilog RTL design - Proven background in Control Path design - Direct experience with On-Chip Bus interfaces (I2C, SPI, MDIO, PCIe, AXI) - Local to the Bay Area Preferred: - Experience with Ethernet Data Path architecture and design - Hands-on experience with Streaming Bus interfaces (AXI-Stream) - Background in FPGA resource management and timing closure - Proficiency in Python, Tcl, or general scripting for EDA tool automation - Lab debugging and validation experience with logic analyzers, oscilloscopes, and vendor-specific debug tools

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