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Arista Networks is seeking an FPGA Design Engineer to join the Hardware Design Engineering team, which develops high-speed networking and Ethernet products for enterprise campuses, hyperscaler data centers, and AI clusters. You will be a core member of the FPGA Design and Verification team, driving the development of high-performance control path FPGAs that power Arista's flagship data center platforms.
You will own the full design lifecycle from gathering architectural requirements and reviewing board schematics through rigorous verification, system bring-up, and production deployment. Working closely with cross-functional hardware, software, and manufacturing engineering teams, you will drive innovation in next-generation system architectures.
Key responsibilities include:
- Developing, integrating, simulating, and verifying Verilog and SystemVerilog RTL code with custom testbench creation
- Executing the full FPGA development flow including synthesis, place and route, timing closure, and in-system hardware debugging
- Collaborating with hardware and software teams on rapid bring-up and debugging of next-generation network switch platforms
- Participating in peer RTL code reviews and PCB schematic/board design reviews
- Developing Python, Tcl, or shell scripts to automate FPGA design workflows and streamline data processing
You will gain expertise in switching architectures (data and control paths), critical I/O interfaces (PCIe, Interlaken, Ethernet PHY/MAC, SMBus, SPI, MDIO, JTAG), Ethernet-based protocols (PTP, sFlow, PoE), real-world FPGA design challenges (timing closure, resource optimization, clock domain crossing), multi-vendor FPGA ecosystems, and cross-functional system design including PCB schematic interpretation and advanced simulation frameworks.
REQUIREMENTS:
- 5+ years of hands-on experience in Verilog/SystemVerilog RTL design
- Proven background in Control Path design
- Direct experience with On-Chip Bus interfaces (I2C, SPI, MDIO, PCIe, AXI)
- Local to the Nashua, NH area
PREFERRED:
- Experience with Ethernet Data Path architecture and design
- Hands-on experience with Streaming Bus interfaces (AXI-Stream)
- Background in FPGA resource management and timing closure
- Proficiency in Python, Tcl, or general scripting for EDA tool automation
- Lab debugging and validation experience using logic analyzers, oscilloscopes, and vendor-specific debug tools
