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Salary: USD 110,000 - 170,000 / annual
Arista Networks is seeking an FPGA Design Engineer to join the Hardware Design Engineering team in Roseville, CA. You will work closely with cross-functional hardware, software, and manufacturing engineering teams to develop high-speed networking and Ethernet products used in enterprise campuses, hyperscaler data centers, and AI clusters.
As a core member of the FPGA Design and Verification team, you will own the full design lifecycle of high-performance control path FPGAs powering Arista's flagship data center platforms. Your responsibilities will include:
• RTL Development & Verification: Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation.
• FPGA Flow Implementation: Execute the full FPGA development flow, including synthesis, place and route, timing closure, and in-system hardware debugging.
• System-Level Integration: Collaborate directly with hardware and software engineering teams to drive rapid bring-up and debugging of next-generation network switch platforms.
• Design & Architecture Reviews: Actively participate in peer RTL code reviews, as well as PCB schematic and board design reviews.
• Toolchain Automation: Develop Python, Tcl, or shell scripts to streamline data processing and automate FPGA design workflows.
You will gain expertise in switching architectures (data and control path), Ethernet-based protocols (PTP, sFlow, PoE), practical FPGA engineering challenges (timing closure, resource optimization, clock domain crossing), multi-vendor FPGA ecosystems, and cross-functional system design including PCB schematics and advanced simulation frameworks.
REQUIREMENTS:
• 2+ years of hands-on experience in Verilog/SystemVerilog RTL design
• Proven background in Control Path design
• Direct experience with On-Chip Bus interfaces (I2C, SPI, MDIO, PCIe, AXI)
• Local to the Bay Area
PREFERRED:
• Experience with Ethernet Data Path architecture and design
• Hands-on experience with Streaming Bus interfaces (AXI-Stream)
• Background in FPGA resource management and timing closure
• Proficiency in Python, Tcl, or general scripting for EDA tool automation
• Lab Debugging & Validation experience with logic analyzers, oscilloscopes, and vendor-specific debug tools
